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w581xx design guide adpcm voice synthesizer ( enhanced powerspeech ? ? ) version e release date: april 1999 - 1 - introduction the w581xx family is an enhanced version of the w528x powerspeech ? synthesizer series. the w581xx family features a adpcm synthesizer and an 8-bit d/a converter to generate various kinds of voice effects. it also provides load and jump commands, eight general and three specific purpose registers, and all other necessary control and timing logic circuit to implement more advanced applications. the w58100 is an emulation chip used for the purpose of demonstrating the w581xx series enhanced powerspeech ? products. the w581xx family includes the w58101, w58102, w58103, w58104, W58105, w58106, w58110, w58115, and the w58120. the rom size of each of these products is shown below: body w58101 w58102 w58103 w58104 W58105 w58106 w58110 w58115 w58120 rom size 80k 160k 240k 320k 512k 768k 1m 1.5m 2m features wide operating voltage range: 2.4 to 5.5 volts 4-bit adpcm synthesis four direct trigger inputs two trigger input, long and short, debounce times up to two led and five stop outputs easily software extendable to 24 matrix trigger inputs flexible functions programmable through the following: - ld (load), jp (jump) commands - eight general purpose registers: r0~r7 - three specific registers: en, stop, and mode - conditional instructions - speech equations - end instruction - output frequency and led flash type setting fading effect (patent pending), and eight levels of spk volume control can be set easily by section control programmable power-on initialization (poi) (can be interrupted by trigger inputs) every led pin can simultaneously drive a maximum of three leds led can be set as a volume control mode output led flash frequency: 3 hz
w581xx design guide - 2 - aud output current: 5 ma poi delay time of 160 ms ensures stable voltage during chip power on can be programmed for the following functions: - interrupt or non-interrupt for each trigger pin; rising or falling edge (this feature determines retriggerable, non-retriggerable, overwrite, and non-overwrite f eatures of each trigger pin) - four playing modes: one shot (os) level hold (lh) single-cycle level hold (s_lh) complete-cycle level hold (c_lh) - stop output signal setting - serial, direct, or random trigger mode setting four frequency options (4/4.8/6/8 khz) and led on/ off control can be set independently in each speech equation go instruction independent control of led 1 and led 2 total of 256 voice group entries available for programming provides the following mask options: - led flash type: synchronous/alternate - led 1 section-controlled: yes/no - led 2 section-controlled/stpc-controlled - led volume-controlled: no/yes - ftest/stpd (note: the ftest function is not provided on the w58100, only on w581xx.) - stpe/busy - normal/cpu provides the following program declarations: - freq0, freq1, freq2, freq3: frequency variable - led0, led1: led on or off - vol0~vol7: fading effect (patent pending)
w581xx design guide - 3 - block diagram (w58100) osc timing generator tg1 tg2 tg4 tg3 led 1 controller stpa stpb synthesizer adpcm converter register spk shift d/a v v dd ss external interface circuit wrp rdp data /disotp led2/stpc stpd stpe/busy /reset pin configuration (w58100) 18 19 20 1 2 3 4 5 6 7 14 15 16 17 11 12 13 8 9 10 tg4 stpe/busy stpd(/ftest) led2/stpc v tg1 tg2 tg3 led1 stpb stpa nc spk v ss dd wrp data rdp /reset /disotp osc * ftest: not provided on w58100, but provided on w581xx
w581xx design guide - 4 - pin description (w58100) no. name i/o function 1 tg1 i trigger input 1 2 tg2 i trigger input 2 3 tg3 i trigger input 3 4 tg4 i trigger input 4 5 led1 o led 1 6 stpb o stop signal b 7 stpa o stop signal a 8 nc o no connected 9 spk o current output for speaker 10 v ss - negative power supply 11 v dd - positive power supply 12 osc i oscillation frequency control, connect rosc to vdd 13 /disotp i disable all of the serial interface pins (low active) 14 /reset i reset pin (low active) 15 led2/stpc o led2 or stop c output 16 stpd(/ftest) o stop d output (ftest not provided on w58100) 17 stpe/busy o stop e or busy signal output 18 *rdp o read pulse clock output for serial interface 19 *data i/o bidirectional data pin for the serial interface 20 *wrp o write pulse clock output for serial interface *: the rdp, wrp, and data pins are only provided on w58100. 1. tg1~tg4 these pins are pulled high internally by an equivalent resistance of around 1m ohm. after being activated these direct trigger inputs start executing the corresponding voice groups, which are located at 0/1/2/3 for falling edge triggers and at 4/5/6/7 for rising edge triggers. the priority is set as: tg1f > tg1r > tg2f > tg2r > tg3f > tg3r > tg4f > tg4r. when more than one trigger is activated, only the one with the highest priority is serviced; all other trigger pins are suppressed. 2. led1, led2 these pins are open-drain outputs to sink current through the leds. 3. stpa~stpe these are inverter-type stop output signals that can be used to drive external peripherals such as transistors, motors, or lamps. they are also useful in keypad scan applications with up to 24 keys.
w581xx design guide - 5 - in keypad matrix applications, tg1~tg4 function as the trigger inputs to initiate the software scan routine. these inputs determine which key has been pressed by determining which row (tg1 ~ tg4) and which column (vss, stpa ~ stpe) has been connected. the 24 key matrix does not require additional components and is shown below: 18 19 20 1 2 3 4 5 6 7 14 15 16 17 11 12 13 8 9 10 tg4 stpe/busy stpd/ftest led2/stpc v tg1 tg2 tg3 led1 stpb stpa nc spk v ss dd wrp data rdp /reset /disotp osc w58100 4. stpe/busy this pin is configured as stpe or busy depending upon the program declaration of this pin. if this pin is not declared as either stpe or busy then it will default to stpe in normal mode and as busy in cpu mode. the busy signal goes high whenever a successful interrupt occurs, whether the interrupt comes from poi, the micro-controller (cpu), or a trigger input. when an interrupt occurs, the busy signal goes high and stays high until the end of the operation. i.e. after encountering an "end" instruction the busy signal will be low. 5. stpd/ftest this pin is configured as a stpd output or as a frequency output test pin, ftest, depending on the program declaration of this pin. after being declared as an ftest pin at the beginning of the program, this pin will generate a constant frequency output during playback. a counter can then be used to test this constant frequency in order to check whether the frequency deviation of this code is normal or abnormal. the constant frequency will be kept at 6k hz, under the condition of the typical master frequency - for example, 3m hz. 6. osc a ring oscillator is used to generate the master frequency of about 3 mhz. this pin is connected with an rosc resistor to vdd providing a bias current for the ring oscillator.
w581xx design guide - 6 - 7. wrp, rdp, and data these three pins are dedicated to the w58100 emulation chip and are used to communicate with external serial memory devices such as flash eproms. using these three pins together with an w58100 chip allows for 100% emulation of code to be used in mass produced chips. 8. /disotp this pin is used to disable the three serial interface pins (wrp, rdp, and data) on the w58100 emulation chip. this allows the programming of a flash eprom without disconnecting the interface pins in advance. this pin can be grounded to program the flash eprom which is bonded on the cob and w58100. this concept is shown in the following diagram: wrp data rdp /disotp wrp data rdp vpp mclk pgm vss vdd w58100 w55412a tg1 osc spk vdd vss writer textool 1 8 1 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 2 3 4 5 6 7 pcb cob ground after programming, the /disotp pin must be floated in order to enable the wrp, data and rdp pins on the w58100. the sound effect of the flash eprom can then be heard. 9. /reset this is an active-low reset input with an internal pull-high resistance of 500k ohm. the falling edge of this pin resets the w581xx ic completely just as if a power-on reset had been performed. the w581xx begins the poi process on the rising edge of this pin. the device may function abnormally and cause unpredictable operation if vdd is not discharged to ground and the w581xx is powered up again. this pin can be used to reset the w581xx. 10. spk the spk pin is a current type voice output connected to the internal d/a converter. the full-scale output of the 8-bit d/a converter is 5ma. this output is sufficient to drive an external 8 ohm speaker by using an external low-power npn transistor with a 120~160 beta value, such as an 8050d, or its equivalent.
w581xx design guide - 7 - functional description 1. instruction sets the w581xx family powerspeech ? program instruction sets include unconditional and conditional instructions. most of these instructions are programmed by writing "ld (load)" and "jp (jump)" commands and by modifying the contents of the r0~r7, en, stop, and mode registers. registers a. r0~r7 register rn (n:0~7) is an 8-bit register that stores the entry values from 0 to 255 voice groups. the structure of this register is shown below: rn: bit: 7 6 5 4 3 2 1 0 the default value of rn is 0. b. en register en is an 8-bit register that stores the rising/falling edge enable or disable status information for all trigger pins. this information determines whether each trigger pin is retriggerable, non-retriggerable, overwrite, or non-overwrite. the 8-bit structure of this register and the rising or falling edge of the triggers corresponding to each bit are shown below: en: bit: 7 6 5 4 3 2 1 0 trigger: 4r 3r 2r 1r 4f 3f 2f 1f the digits 1 to 4 represent tg1 to tg4, respectively; "r" represents the rising edge; and "f" represents the falling edge. when any one of the eight bits is set to "1," the rising or falling edge of the corresponding trigger pin can be enabled, interrupting the current state. the default value of en register is "1111 1111"?. c. stop register the stop register stores stop output status information to determine the voltage level of each stop output pin. the 8-bit structure of this register and the stop output pin corresponding to each bit are shown below:
w581xx design guide - 8 - stop: bit: 7 6 5 4 3 2 1 0 stop: x x x stpe stpd stpc stpb stpa "x" indicates a "don't care" bit. the default value of the stop register is "1111 1111" d. mode register the mode register is used to store operand information to select the various operating modes as shown below. mode: bit: 7 6 5 4 3 2 1 0 mode: flash/dc led2/stpc x long/short debounce time x x x x a "1" for one of these bits selects the first of the pair of modes indicated; a "0" selects the second of the pair. bit 7 is used to determine the output status of led1 and/or led2: flash alternate or synchronous output (by mask option), or dc (led will be lit constantly without flashing). bit 6 determines whether pin15 acts as a led output pin or stop output pin. bit 4 is used to determine whether the debounce time for all trigger inputs is long (around 45 ms) or short ( around 350 m s) time. the default value of the mode register is "11x1 xxxx", that is "flash, led2, x, long debounce time, x,x,x,x" commands a. unconditional instructions load (ld) command: this command can load value or operand data into the rn (n:0~7), en, stop, or mode register. ld rn, value: this instruction is used to load a voice group entry value into register rn (n:0~7), as shown in the following example. example:
w581xx design guide - 9 - ld r0, 167 0xa7 1 0 1 0 0 1 1 1 b (hexadecimal) (decimal) value: 0 to 255 ld en, operand: this instruction is used to define the trigger interrupt settings by loading the operand message into register en. the following example illustrates how the settings are defined. example: ld en, 0x41 0 1 0 0 0 0 0 1 0100 0001 (binary) (hexadecimal) tg: 4r 3r 2r 1r 4f 3f 2f 1f group: 7 6 5 4 3 2 1 0 a. when the rising edge of tg3 (3r) is activated, the en register will cause tg3 to interrupt the current playing state and jump immediately to voice group 6, the voice group that corresponds to 3r. b. when the falling edge of tg1 goes active, the en register will cause tg1 to interrupt the current playing state and jump immediately to voice group 0, the voice group that corresponds to 1f. c. no action will be taken when the other trigger pins are pressed, because the corresponding bits are set to "0." ld stop, operand: this instruction loads the operand message into the stop register to set the output levels of the stop signals. when a particular stop bit is set to "0," the corresponding stop signal will be an active low output. example: ld stop, 0x53 stpc stpb stpa 0 1 0 1 0 0 1 1 x x x stpe stpd stop: a. the stpa, stpb and stpe output signals will be high outputs. b. the stpc and stpd output signals will be low outputs. c. the bit6 "1" is a "don't care" bit and so has no effect on the stop signal output setting.
w581xx design guide - 10 - ld mode, operand: this instruction is used to select among various operating modes. it loads an operand message into the mode register to select one mode from each of several pairs of modes. a "1" for one of these bits selects the first of the pair of modes indicated; a "0" selects the second of the pair. the following example describes the mode setting of the w581xx product. example: ld mode, 0xd0 1 1 0 1 0 0 0 0 mode: flash led2 long time don't care don't care a. the led is set as a flash type, with the flash frequency 3 hz. b. pin 15 (led2/stpc) is configured as the led2 output pin. c. the bit5 is a "do not care" bit because the 4th pin of w581xx is fixed as tg4 pin. d. the debounce time of the trigger inputs is set to long time (around 45 ms) jump (jp) command: jp value: instructs the device to jump directly to the voice group corresponding to the value indicated. the voice group value may range from 0 to 127. jp rn (n:0~7): instructs the device to jump to whatever voice group is indicated by the value currently stored in register rn. b. conditional instructions: conditional instructions are executed only when the conditions specified in the instructions hold. the conditional instructions are listed below. an explanation of the notation used in the instructions follows. (note: there are no conditional instructions for ld mode.) load (ld) command: ld rn (n:0~7), value @last: load the voice group entry value into rn when the last global repeat sound cycle is finished.
w581xx design guide - 11 - ld rn (n:0~7), value @tgm_high (or_low): if the m-th (m: 1 to 4) trigger pin status is kept at "high" (or "low") voltage level, then load the value into rn register. ld en, operand @last: load the operand message into the en register when the last global repeat sound cycle is finished. ld stop, operand @last: load the operand message into the stop register when the last global repeat sound cycle is finished. jump (jp) command: jp value @last: when the last global repeat sound cycle is finished, jump to the group entry value indicated (range: 0 to 127) and begin execution. jp rn (n:0~7) @last: when the last global repeat sound cycle is finished, jump to the group entry value indicated by the rn register and begin execution. jp value @tgm _ _ high (or _low): if the m-th (m: 1 to 4) trigger pin is kept at "high" (or "low") voltage level, then jump to the indicated value (range: 0 to 127) and begin execution. jp rn (n:0~7) @tgm _ _ high (or _low): if the m-th (m: 1 to 4) trigger pin is kept at "high" (or "low") voltage level, then jump to the group entry value indicated by the rn register and begin execution. c. end instruction: end: this command instructs the chip to immediately cease all activity.
w581xx design guide - 12 - d. instruction set list: instruction range description default value unconditional ld rn, value (n:0~7) 0 - 255 rn ?? value 0000 0000 ld en, operand - en ?? operand 1111 1111 ld stop, operand - stop ?? operand xxx1 1111 ld mode, operand - mode ?? operand 11x1 xxxx jp value 0 - 127 jump to the group entry value indicated - jp rn (n:0~7) 0 - 255 jump to the group entry indicated by rn - conditional ld rn, value @last (n:0~7) 0 - 255 if last global repeat finished, rn ?? value - ld rn, value @tgm_high (n:0~7) 0 - 255 if tgm (m:1- 4 ) status is high level, rn ?? value - ld rn, value @tgm_low (n:0~7) 0 - 255 if tgn (m:1-4 ) status is low level, rn ?? value - ld en, operand @last - if last global repeat finished, en ?? operand - ld stop, operand @last - if last global repeat finished, stop ?? operand - jp value @last 0 - 127 if last global repeat finished, jump to the group entry value indicated - jp rn @last (n:0~7) 0 - 255 if last global repeat finished, jump to the group entry value indicated in rn - jp value @tgm_high 0 - 127 if tgm (m: 1- 4) status is high level, jump to the group entry value indicated - jp value @tgm_low 0 - 127 if tgm (m: 1- 4) status is low level, jump to the group entry value indicated - jp rn @tgm_high (n:0~7) 0 - 255 if tgm (m: 1- 4) status is high level, jump to the group entry value indicated in rn. - jp rn @tgm_low (n:0~7) 0 - 255 if tgm (m: 1 - 4) status is low level, jump to the group entry value indicated in rn - end end stop all activity and enter standby state -
w581xx design guide - 13 - 2. mask option description the mask options of the w581xx enhanced powerspeech ? are used to select features that cannot be programmed through the chip's registers. the w581xx provides seven mask options, which are listed in the following table: mask option instruction demo chip option led flash type (asynchronous/synchronous) led_asyn; (default) led_syn - led volume controlled (no/yes) led_vol_off; (default) led_vol_on if led_vol_on is set, the other mask options will be redundant led1: section-controlled (yes/no) led1_s_ctl; (default) led1_s_off - led2: section-controlled /stpc-controlled led2_s_ctl; (default) led2_stc_ctl - the 16th pin defined stpd ; (default) ftest for w58100 only stpd is provided the 17th pin defined stpe; (default) busy if in cpu mode, the default item is busy. normal/cpu mode setting normal; (default) cpu - notes: 1.the demo chip for the w581xx series is the w58100. 2. mask options can be configured automatically by the w58100. 3. speech equation description speech equations are used to define the combination of playback sounds. the following is an example of a speech equation format: i:n h4+m1*(a_flv+m2*(b_flv+m3*(c_flv+m4*d_flv)))+...t4 m4*[1ffff] end where
w581xx design guide - 14 - (1). i defines the group number (from 0 to 255). (2). n defines the number of global repeats (from 1 to 16). (3). m1, m2, m3 and m4 define the number of local repeats (from 1 to 7). (4). a, b, c, and d are files containing adpcm converted voice data. (5). _flv is the section control setting, for which the parameters f, l and v are as follows: f: sampling frequency define (default value: f=2) f 3 2 1 0 frequency 8 khz 6 khz 4.8 khz 4 khz i: led status define (default value: l=0) l 1 0 led status on off v: fading effect define (default value: v=7) the max. value of the voice is v=7, that is the full scale of the sound. the min. value is v=0, that is 0.1 times of the full scale of the sound. the volume value from large to small is 7> 6> 5> 4> 3> 2> 1> 0. note 1: if the section control setting is not defined, the default values are used. for example, in the speech equation h4+a+t4, if the a sound is played, the default values are used. these values are: 6k hz sampling frequency (f=2), led off (l=0), and maximum volume output (v=7). note 2: if the section control setting is defined, both the f and l digits must be defined together. the v digit is optional. for example: 1. h4+a_2+t4: this is a wrong speech equation since only one digit (f) of section control is defined. 2. h4+a_21+t4: this is a correct speech equation with section control. the sampling frequency is 6k hz (f=2), the led is on (l=1), and the volume is maximum value (v=7, the default value). 3. h4+a_210+t4: this is a complete speech equation with section control. the sampling frequency is 6k hz (f=2), the led is on (l=1), and the volume is minimum value (v=0). (6). [1ffff] is a period of silence of length 1ffff (around 5.46 seconds) under the 6k hz sampling frequency condition. the maximum silence length in one "[ ]" is [fffff], that is 1m bits, around 43.69 seconds under the 6k hz sampling frequency condition. the silence can't be placed between voices and h4/t4 that will generate a little noise. it is necessary to place it on one line as above example that will gain a good silence.
w581xx design guide - 15 - (7). h4 and t4 are the head file and tail file with 4-bit adpcm data format. these two files can be used to eliminate the popping sound which may occur when the sound starts and stops. the following is a sample waveform: 0.25kbit 0.25kbit h4 t4 0 1/2v v 0.25kbit 0.25kbit h4 t4 [silence] if the voice (h4+....+t4) doesn't play smoothly, then nh4 and nt4 can be used to displace h4 and t4. by using nh4 and nt4 smooth playing voices can be created, however more rom memory is required (around 0.66kbits). (8). flexible combination of unlimited "( )": this feature can be used in writing speech equations. this feature reduces program writing time but does not save program memory. for example: eq1: h4+2*(a+2*(b+2*(c+3*d)))+t4 eq2: h4+a+b+c+3*d+c+3*d+b+c+3*d+c+3*d+a+b+c+3*d+c+3*d+b+c+3*d+c+3*d+t4 these two speech equation are the same. after compiling, these two speech equations will occupy the same program memory size. note that eq1 is much easier to write and understand than eq2. there is no limit in the number of "( )". however, each pair of "( )"? must be written on the same line. 4. programmable power-on initialization whenever the w581xx enhanced powerspeech ? is powered on, the programs contained in the 32nd voice group will be executed immediately. programs can therefore be written into this group to set the initial power-on state. if the user does not wish to execute any programs at power-on, an "end" instruction should be entered in group 32. 5. powerspeech ? ? program format the w581xx powerspeech ? has a programming language to define the product functions. an example of the w581xx powerspeech ? program format is shown below. explanatory notes follow the example (for reference only)
w581xx design guide - 16 - led_asyn led1_s_ctl led2_s_ctl led_vol_off (1) (2) (6) 32: 5 h4+sn_013+sn_20+sn_316+t4 end 0: 3 h4+s11+s2+t4 end 2: ld r0, 64 ld en, 0x00 ; disable all triggers ld mode, 0x90 ; led flash, stop c, 20 ms ld stop, 04 ; stop c = 1, ; stop a, stop b, stop d, stop e = 0 (4) (5) (7) (8) (9) end W58105 ; (default)/ [led_syn ] ; (default)/ [led1_s_off ] ; (default)/ [led2_stc_ctl ] ; (default)/ [led_vol_on ] led0 ; (default)/ [led1 ] freq2 ; (default)/ [freq0, freq1, freq3 ] (3) vol7 ; (default)/ [vol0~vol6] stpd stpe normal ; (default)/ [ftest ] ; (default)/ [busy ] ; (default)/ [cpu ] [1ff] notes: (1) bodies: the user must first define the enhanced powerspeech ? body to be used, or else an error message will appear during compiation. the enhanced powerspeech ? bodies include the following: w581xx: w58101, w58102, w58103, w58104, W58105, w58106, w58110, w58115, and w58120 (2) mask options: see above description. (3) declarations: state the output frequency, led on/off state and volume variable, as follows: led on/off: -- led0: led off (default) -- led1: led on output frequency: -- freq0: 4khz -- freq1: 4.8 khz -- freq2: 6 khz (default)
w581xx design guide - 17 - -- freq3: 8 khz volume variable: -- vol0: (minimum) 0.1 times volume of the full scale of the sound -- vol1 -- vol2 -- vol3 -- vol4 -- vol 5 -- vol6 -- vol7: (maximum) the full scale of the sound (default) (4) program body : write application program and speech operations, including the following: define entry point of speech group. determine the number of global repeats. describe speech equations. define the register values and instructions. note 1: the maximum program memory size that can be used by the w581xx is 64k bits. note 2: every go instruction occupies 48 bits, and every group entry value (0~255) occupies 16 bits. therefore, a total of around 1,300 go instructions can be used in a program. note 3: the go instruction includes the following contents: (a). instruction set: like "ld r0, xx", "jp r3 @tg2_low" ...etc. (b). end instruction: end (c). every adpcm file for the speech equations. for example, in the speech equation: h4+a+b_217+c+t4, there are a total of 5 go instructions: h4, a, b_217, c, and t4. these go instructions do not include the mask option and declaration instructions. for example: (for reference only) w 58105 ; body define, 0 go instruction led_syn ; mask option, 0 go instruction led1_s_ctl ; mask option, 0 go instruction freq3 ; declaration, 0 go instruction vol5 ; declaration, 0 go instruction 32: ; poi group entry, 16 bits ld en, 0x0f ; 48 bits, 1 go instruction ld stop, 0x10 ; 1 go instruction end ; end instruction, 1 go instruction 0:3 ; group entry, 16 bits.
w581xx design guide - 18 - ; the global repeat 3 occupied 4 bit rom size included in the group entry. ld en, 0x00 ; 1 go instruction ld stop, 0x1f ; 1 go instruction h4+3*a+b_217+c+t4 ; speech equation, total with 6 go [1fff] ; instructions. include: ; h4, 3*a, b_217, c, [1fff], and t4. ld stop, 0x10 ; 1 go instruction ld en, 0x0f ; 1 go instruction end ; 1 go instruction 1: ; 16 bits h4+a+b+c_30+d+e+t4 ; 8 go instructions: [1fff] ; h4, a, b, c_30, [1fff], d, e, and t4 end ; 1 go instruction 2: ; 16 bits jp 100 @tg4_low ; 1 go instruction end ; 1 go instruction 100: ; 16 bits h4+3*(a+2*b)+t4 ; equal to: h4+a+2*b+a+2*b+a+2*b+t4, total with 8 go ; instructions. end ; 1 go instruction in the program example shown above, there are a total of 34 go instructions and 101 group entries (= 100+1, because the maximum group entry to be used is 100). the total program memory size for this program is 3,248 bits (34*48+101*16=3248). note 4: to use the 64k bits program memory size more efficiently, the following suggestions can be followed: (a). the voice groups should b e used consecutively and without skipping. for example: 0, 1, 2, 3....255, is better than 0, 1, 100, 150... 255. (b). if the program includes several voice groups, then the voice group with the most go instructions should be placed at the end of the program. (5) group body: define the voice group entry point. product group entry points tg h/w entry points power-on entry point w581xx 0-255 0-7 32 (6) note: a semicolon (";") is used to distinguish characters that are not part of the program. characters written to the right of the semicolon are not considered part of the program. (7) global repeat: the global repeat instruction is "n" where n is from 1 to 16. this instruction must be placed on the same line as the group entry point.
w581xx design guide - 19 - (8) speech equation: these are used to define the combination of playback sounds. (9) blank: a voice group entry point must be followed by one full blank line without any instructions or speech equations. 7. cpu interface the w581xx can communicate with an external microprocessor through a simple serial cpu interface. the voice group transmitted from cpu must between 128 and 255. it is shown below: tg1 tg2 (data) (clock) deb t crd t s t h t busy d t pl t ph t clr t tclr > tdeb, tdeb = 256/fs or 2/fs depend on long or short debounce, which fs is the speech sampling rate of last synthesized speech. fs default value is 6khz when power on or after reset. tcrd > 5us ts > 500ns th> 50ns tpl > 500ns tph > 500 ns tzero < 128/fs or 1/fs depend on long or short debounce td < 50 ns tg1 tg2 (data) (clock) deb t crd t clr t zero t note :
w581xx design guide - 20 - 1. tdeb means the "debounce time" which can be "long" or "short", depending on bit4 of the mode register. if the mode register has a "1" in bit4, then the debounce time will be set to "long" if bit4 is "0",? then the debounce time will be set to "short". in case of last synthesized speech sampling rate is 6khz, for long debounce tdeb = 256/6k = 42.7ms, for short debounce tdeb = 2/6k = 333us. 2. only when tclr is longer than tdeb, the receiving data counter of w581xx can be clear to zero. considering about the speech sampling frequency may shift due to the deviation of component or voltage, at least 20% mark up,i.e. 42.7ms * (1 + 20%) = 51.2 ms for long debounce when the last synthesized speech sampling rate is 6khz, is suggested to guarantee the success of debounce. for short debounce at 6khz speech sampling rate, 333us * (1 + 20%) = 400 us were recommended. 3. tcrd is the "cpu reset delay" time. 4. during data transfer phase, tzero, the consecutive low state on tg1(data), could not be longer than half of debounce time tdeb, otherwise it may be treated as a debounce and then reset the receiving data counter. for the same reason of possible frequency shift just like tclr, 20% margin were suggested. at fs = 6khz and long debounce, the consecutive low state on tg1(tzero) can not more than 0.5 * tdeb * (1 - 20%) = 0.5 * 42.7 ms * 0.8 = 17 ms for long debounce and 0.5 * 333us * (1-20%) = 133 us for short debounce. to program w581xx in cpu mode, the cpu keyword must be added and tg1f/ tg1r/ tg2f/ tg2r must be disabled including the directly interrupt and condition commands. so in the cpu mode the "@tg1_high/low" and "@tg2_high/low" are illegal and bit0, bit1, bit4 and bit5 of the en register must be set to "0". the following example shows this: (for reference only) W58105 cpu ; reserved word, for cpu mode mask option led1_s_ctl led2_stc_ctl 32: ld en,0x0c ; disable tg1f/tg1r/tg2f/tg2r ld mode,0x8f ; bit4 of the mode register is 0 ; so the debounce time is selected "short" (arround 350 m s) end 0: 1: 4: 5: e nd 162: ; cpu interrupt h4+voice1+t4 end the waveform must be sent from the external m c through tg1 and tg2 to control the playing of the voice group. the waveform looks like this: in the program example (for reference only) shown above, the m c will transfer the number 162 to interrupt w581xx. the number 162 (decimal) is equal to 10100010b (binary).
w581xx design guide - 21 - tg1 tg2 (data) (clock) 0 1 0 0 0 1 1 0 msb lsb <1> <2> <3> <4> deb t crd t <1> when tg1 is pulled low, the w581xx stops playing voice or instructions and waits for data from the external m c. <2> when tg1f debounces ok, the w581xx clears the cpu receiving buffer. <3> 8-bit data are transferred by tg1 (data) and tg2 (clock). the first bit of the data to be sent is the lsb . <4> tg1 returns high and starts the cpu interrupt. in this case W58105 will play the h4+voice1+t4 sections and the busy pin is pulled high until the "end" instruction is reached. example: <1> micro controller program (used w74c250 as the controller) ; w581 cpu mode test program ; w581 chosen the long debounce time ; w74c260 with the rc oscillator: 11 kohm rosc ; clock pin connect to re0 ; data pin connect to re1 ; busy pin connect to rc3 addr_h equ ram20 ; store the w581cpu data, high byte addr_l equ ram21 ; low byte ;................................................ org 000h mov ief,#00000000b ; disable all interrupt mov hef,#00000000b mov pef,#0000b jmp begin org 004h ; divider0 rtn org 008h ; timer0 rtn org 00ch jmp portrc org 014h ; divider1 rtn org 020h ; timer1
w581xx design guide - 22 - rtn ;................................................ begin: mov pm0,#1100b ; rc.3 as w581 busy pin mov pm1,#1111b ; ra is input pins mov pm2,#1111b ; rb is input pins mov wre,#1111b ; data and clock pins pulled high mov re,wre mov ra,wre mov rb,wre ;........................................................ mov ram10,#2h ; power on waiting 200ms in order to ddd5b: mov ram11,#0fh ; complete w581 setup procedure ddd4b: mov ram12,#0fh ddd3b: mov ram13,#0fh ddd2b: mov ram14,#0fh ddd1b: dec ram14 jnz ddd1b dec ram13 jnz ddd2b dec ram12 jnz ddd3b dec ram11 jnz ddd4b dec ram10 jnz ddd5b ;........................................................ mov addr_h,#0010b ; send group 32 for poi mov addr_l,#0000b call playsound ;serial output subroutine mov ief,#00000100b ; enable interrupt port rc mov hef,#00000100b mov pef,#1000b set128: mov addr_h,#1000b mov addr_l,#00 00b sleep: en int hold inc addr_l ; increment w581 address data mov wrf,addr_h ; from 128 to 255 adcr wrf,#0 mov addr_h,wrf jz set128 jmp sleep ;................................................ portrc: mova wre,rc xrl wre,#1111b jb3 w581cpu
w581xx design guide - 23 - over_rc: clr psr0 rtn w581cpu: call playsound ; w581 play sound jmp over_rc ;................................................ playsound: mov wr8,#3 ; retransmit 3 times send_again: mov wr0,#1 ; make tg1 low mov re,wr0 mov ram10,#08h ; tg1 low for >70ms to fit the long debounce time spec. ddd4a: mov ram11,#0fh ddd3a: mov ram12,#0fh ddd2a: mov ram13,#0fh ddd1a: dec ram13 jnz ddd1a dec ram12 jnz ddd2a dec ram11 jnz ddd3a dec ram10 jnz ddd4a mov wr0,#3 ; tcrd -> cpu reset time > 5 m s mov re,wr0 nop nop nop nop ;................................................ mov acc,addr_l ; lsb first send jb0 bit0_h mov wr0,#0 ; bit0 <-- low mov re,wr0 mov wr0,#1 nop mov re,wr0 jmp bit1 bit0_h: ; bit0 <-- high mov wr0,#2 mov re,wr0 mov wr0,#3 nop mov re,wr0 bit1: mov acc,addr_l jb1 bit1_h mov wr0,#0 ; bit 1 <-- low mov re,wr0
w581xx design guide - 24 - mov wr0,#1 nop mov re,wr0 jmp bit2 bit1_h: ; bit 1 <-- high mov wr0,#2 mov re,wr0 mov wr0,#3 nop mov re,wr0 bit2: mov acc,addr_l jb2 bit2_h mov wr0,#0 ; bit 2 <-- low mov re,wr0 mov wr0,#1 nop mov re,wr0 jmp bit3 bit2_h: ; bit 2 <-- high mov wr0,#2 mov re,wr0 mov wr0,#3 nop mov re,wr0 bit3: mov acc,addr_l jb3 bit3_h mov wr0,#0 ; bit 3 <-- low mov re,wr0 mov wr0,#1 nop mov re,wr0 jmp bit4 bit3_h: ; bit 3 <-- high mov wr0,#2 mov re,wr0 mov wr0,#3 nop mov re,wr0 bit4: mov acc,addr_h jb0 bit4_h mov wr0,#0 ; bit 4 <-- low mov re,wr0 mov wr0,#1 nop mov re,wr0 jmp bit5 bit4_h: ; bit 4 <-- high
w581xx design guide - 25 - mov wr0,#2 mov re,wr0 mov wr0,#3 nop mov re,wr0 bit5: ; for next nibble addr_h mov acc,addr_h jb1 bit5_h mov wr0,#0 ; bit 5 <-- low mov re,wr0 mov wr0,#1 nop mov re,wr0 jmp bit6 bit5_h: ; bit 5 <-- high mov wr0,#2 mov re,wr0 mov wr0,#3 nop mov re,wr0 bit6: mov acc,addr_h jb2 bit6_h mov wr0,#0 ; bit 6 <-- low mov re,wr0 mov wr0,#1 nop mov re,wr0 jmp bit7 bit6_h: ; bit 6 <-- high mov wr0,#2 mov re,wr0 mov wr0,#3 nop mov re,wr0 bit7: mov acc,addr_h jb3 bit7_h mov wr0,#0 ; bit 7 <-- low mov re,wr0 mov wr0,#1 nop mov re,wr0 jmp oversend bit7_h: ; bit 7 <-- high mov wr0,#2 mov re,wr0 mov wr0,#3 nop mov re,wr0
w581xx design guide - 26 - oversend: mov wr0,#3 mov re,wr0 mov ram12,#0fh ; delay >200us d2a: mov ram13,#0fh d1a: dec ram13 jnz d1a dec ram12 jnz d2a mova wre,rc ; check busy pin high or not skb3 wre jmp next_time ; if busy pin still low send the data again rtn next_time: dskz wr8 jmp send_again rtn ;................................................ end tg1 tg2 w581xx aud led1 busy stb v dd (clock) (data) re0 re1 rc3 w74c250 <2> w581xx cpu mode program w58104 cpu poi: ld mode,0xff ld en,0x00 end 128: h4+1+2+8+t4 end 129: h4+1+2+9+t4 end 130: h4+1+3+0+t4 end 131: h4+1+3+1+t4 end 132: h4+1+3+2+t4 end 133: h4+1+3+3+t4
w581xx design guide - 27 - end 134: h4+1+3+4+t4 end 135: h4+1+3+5+t4 end 136: h4+1+3+6+t4 end 137: h4+1+3+7+t4 end 138: h4+1+3+8+t4 end 139: h4+1+3+9+t4 end 140: h4+1+4+0+t4 end 141: h4+1+4+1+t4 end 142: h4+1+4+2+t4 end 143: h4+1+4+3+t4 end 144: h4+1+4+4+t4 end 145: h4+1+4+5+t4 end 146: h4+1+4+6+t4 end 147: h4+1+4+7+t4 end 148: h4+1+4+8+t4 end 149: h4+1+4+9+t4 end 150: h4+1+5+0+t4 end 151: h4+1+5+1+t4 end 152: h4+1+5+2+t4 end 153: h4+1+5+3+t4 end 154: h4+1+5+4+t4 end 155: h4+1+5+5+t4 end 156: h4+1+5+6+t4 end 157: h4+1+5+7+t4 end 158: h4+1+5+8+t4 end 159: h4+1+5+9+t4 end 160: h4+1+6+0+t4 end 161: h4+1+6+1+t4 end 162: h4+1+6+2+t4 end 163: h4+1+6+3+t4 end 164: h4+1+6+4+t4 end 165: h4+1+6+5+t4 end 166: h4+1+6+6+t4 end
w581xx design guide - 28 - 167: h4+1+6+7+t4 end 168: h4+1+6+8+t4 end 169: h4+1+6+9+t4 end 170: h4+1+7+0+t4 end 171: h4+1+7+1+t4 end 172: h4+1+7+2+t4 end 173: h4+1+7+3+t4 end 174: h4+1+7+4+t4 end 175: h4+1+7+5+t4 end 176: h4+1+7+6+t4 end 177: h4+1+7+7+t4 end 178: h4+1+7+8+t4 end 179: h4+1+7+9+t4 end 180: h4+1+8+0+t4 end 181: h4+1+8+1+t4 end 182: h4+1+8+2+t4 end 183: h4+1+8+3+t4 end 184: h4+1+8+4+t4 end 185: h4+1+8+5+t4 end 186: h4+1+8+6+t4 end 187: h4+1+8+7+t4 end 188: h4+1+8+8+t4 end 189: h4+1+8+9+t4 end 190: h4+1+9+0+t4 end 191: h4+1+9+1+t4 end 192: h4+1+9+2+t4 end 193: h4+1+9+3+t4 end 194: h4+1+9+4+t4 end 195: h4+1+9+5+t4 end 196: h4+1+9+6+t4 end 197: h4+1+9+7+t4 end 198: h4+1+9+8+t4 end 199: h4+1+9+9+t4 end 200:
w581xx design guide - 29 - h4+2+0+0+t4 end 201: h4+2+0+1+t4 end 202: h4+2+0+2+t4 end 203: h4+2+0+3+t4 end 204: h4+2+0+4+t4 end 205: h4+2+0+5+t4 end 206: h4+2+0+6+t4 end 207: h4+2+0+7+t4 end 208: h4+2+0+8+t4 end 209: h4+2+0+9+t4 end 210: h4+2+1+0+t4 end 211: h4+2+1+1+t4 end 212: h4+2+1+2+t4 end 213: h4+2+1+3+t4 end 214: h4+2+1+4+t4 end 215: h4+2+1+5+t4 end 216: h4+2+1+6+t4 end 217: h4+2+1+7+t4 end 218: h4+2+1+8+t4 end 219: h4+2+1+9+t4 end 220: h4+2+2+0+t4 end 221: h4+2+2+1+t4 end 222: h4+2+2+2+t4 end 223: h4+2+2+3+t4 end 224: h4+2+2+4+t4 end 225: h4+2+2+5+t4 end 226: h4+2+2+6+t4 end 227: h4+2+2+7+t4 end 228: h4+2+2+8+t4 end 229: h4+2+2+9+t4 end 230: h4+2+3+0+t4 end 231: h4+2+3+1+t4 end 232: h4+2+3+2+t4 end 233: h4+2+3+3+t4
w581xx design guide - 30 - end 234: h4+2+3+4+t4 end 235: h4+2+3+5+t4 end 236: h4+2+3+6+t4 end 237: h4+2+3+7+t4 end 238: h4+2+3+8+t4 end 239: h4+2+3+9+t4 end 240: h4+2+4+0+t4 end 241: h4+2+4+1+t4 end 242: h4+2+4+2+t4 end 243: h4+2+4+3+t4 end 244: h4+2+4+4+t4 end 245: h4+2+4+5+t4 end 246: h4+2+4+6+t4 end 247: h4+2+4+7+t4 end 248: h4+2+4+8+t4 end 249: h4+2+4+9+t4 end 250: h4+2+5+0+t4 end 251: h4+2+5+1+t4 end 252: h4+2+5+2+t4 end 253: h4+2+5+3+t4 end 254: h4+2+5+4+t4 end 255: h4+2+5+5+t4 end 8. programming examples (for reference only) this section presents several programming examples for the w581xx enhanced powerspeech ? chips. user programs should be written in ascii code using a text editor. after compiling, the sound effects resulting from the programs can be tested by using a winbond demo board. example1: four playing mode settings: a. one-shot trigger mode 0: ; tg1 falling edge group entry point ld en, 0x01 ; enable tg1 falling edge input only h4+sound+t4
w581xx design guide - 31 - end the timing diagram for this example is shown below: case 1: tg1: aud: sound 1 case 2: tg1: aud: sound 1 b. level hold trigger mode 0: ; tg1 falling edge group entry point ld en, 0x11 ; enable tg1 falling and rising edge input h4+sound1+t4 jp 0 4: ; tg1 rising edge group entry point end the timing diagram is shown below: stop immediately s1 stop immediately s1 case 1: tg1: aud: case 2: tg1: aud: c. completed cycle level hold 0: ; tg1 falling edge group entry point ld en, 0x01 ; enable tg1 falling edge input only h4+sound1+t4 jp 0 @tg1_low ; if tg1 state is low, jump to 0 entry point end the timing diagram is shown below:
w581xx design guide - 32 - case 1: tg1: aud: case 2: tg1: aud: s1 s1 s1 d. single cycle level hold 0: ; tg1 falling edge group entry point ld en, 0x11 ; enable tg1 falling and rising edge input h4+sound1+t4 end 4: end the timing diagram is shown below: stop immediately case 1: tg1: aud: case 2: tg1: aud: s1 example 2: retriggerable and non-retriggerable setting a. retriggerable: 0: ld en, 0x01 . . . end the timing diagram is shown below: tg1: aud: sound 1 sound 1 restart restart b. non-retriggerable:
w581xx design guide - 33 - 0: ld en, 0x00 . . . ld en, 0x11 end the timing diagram is shown below: tg1: aud: sound 1 sound 1 example 3: serial playing mode (5 segments) W58105 32: 10: ld r0, 8 ld r0, 11 ld en, 0x01 h4+s3+t4 end end 0: 11: jp r0 ld r0, 12 8: h4+s4+t4 ld r0, 9 end h4+s1+t4 12: end ld r0, 8 9: h4+s5+t4 ld r0, 10 end h4+s2+t4 end the timing diagram is shown below: tg1 aud 1 2 3 5 1 s1 s2 s3 s1 s5
w581xx design guide - 34 - example 4: random (1) W58105 32: 18: ld en, 0x01 h4+s1+t4 ld r0, 8 ld r0, 9 end jp 31 0: 19: ld en, 0x00 h4+s2+t4 jp r0 ld r0, 8 8: jp 31 jp 18 @tg1_high 20: 9: h4+s3+t4 jp 19 @tg1_high ld r0, 11 10: jp 31 jp 20 @tg1_high 21: 11: h4+s4+t4 jp 21 @tg1_high ld r0, 10 jp 8 31: ld en, 0x01 end the timing diagram is shown below: tg1 aud 1 2 3 5 1 s3 s1 s4 s2 s4 ... ... example 5: random (2) W58105 32: 8: ld en, 0x11 h4+s4+t4 end end 0: 9: ld r0, 8 h4+s1+t4 [300] end ld r0, 9 10: [300] h4+s5+t4
w581xx design guide - 35 - ld r0, 10 end [300] 11: ld r0, 11 h4+s3+t4 [300] end ld r0, 12 12: [300] h4+s2+t4 jp 0 end 4: jp r0 the timing diagram is shown below: tg1 aud 1 2 3 5 1 s3 s1 s4 s2 s5 ... ... 7. application examples (for reference only) the following paragraph presents several special application examples. example 1: power-on trigger: if one of the trigger pins is grounded, then the sound corresponding to that trigger will be played out at power-on. program: W58105 9: 32: h4+s2+t4 ld en, 0x00 ld en, 0x0f jp 8 @tg1_low end jp 9 @tg2_low 2: jp 10 @tg3_low 10 jp 11 @tg4_low h4+s3+end ld en, 0x0f ld en, 0x0f 0: end 8: 3: h4+s1+t4 11: ld en, 0x0f h4+s4+t4 end ld en, 0x0f 1: end
w581xx design guide - 36 - application circuit: led1 sta stb tg1 tg2 tg3 w581xx aud tg4 v dd vdd example 2: 8 tg input application: in this application, the 4 trigger inputs are expanded to 8 trigger inputs. program: W58105 32: ld mode, 0xa0 ld stop, 0x00 ; stpa set to low level ld en, 0x0f ; one shot play mode end 0: ld stop, 0x01 ; stpa set to high level jp 8 @tg1_high ; check high h4+v1+t4 ; play v1 ld stop, 0x00 ; stpa set to low level end 8: ; pseudo trigger pin h4+v2+t4 ; play v2 ld stop, 0x00 ; stpa set to low level end 1: ld stop, 0x01 ; stpa set to high level jp 9 @tg2_high ; check high h4+v3+t4 ; play v3 ld stop, 0x00 ; stpa set to low level end 9: ; pseudo trigger pin
w581xx design guide - 37 - h4+v4+t4 ; play v4 ld stop, 0x00 ; stpa set to low level end 2: ld stop, 0x01 ; stpa set to high level jp 10 @tg3_high ; check high h4+v5+t4 ; play v5 ld stop, 0x00 ; stpa set to low level end 10: ; pseudo trigger pin h4+v6+t4 ; play v6 ld stop, 0x00 ; stpa set to low level end 3: ld stop, 0x01 ; stpa set to high level jp 11 @tg4_high ; check high h4+v7+t4 ; play v7 ld stop, 0x00 ; stpa set to low level end 11: ; pseudo trigger pin h4+v8+t4 ; play v8 ld stop, 0x00 ; stpa set to low level end application circuit tg1 tg2 tg3 w581xx v1 v2 v3 aud tg4 v4 v5 v6 v7 v8 led1 sta stb v dd delay time: v1~v8: 2ms + debounce time
w581xx design guide - 38 - example 3: fading effect application this program will play the "voice" with a reducing volume. the stop signals will be turned off (1: on, 0: off) one by one. program: W58105 32: ld mode, 0x10 ; pin15 set as stpc output ld stop, 0x00 ; set stpa, stpb, and stpc = 0 ld en, 0x0f end 0: ld stop,0x1f ; stpa, b, c, d, e turn on h4+voice_217 ; sample rate= 6k, led1 turn on, volume= 7 (the biggest) ld stop,0x1e ; stpb, c, d, e turn on, stpa turn off voice_306 ; sample rate= 8k, led1 turn off, volume= 6 voice_215 ; sample rate= 6k, led1 turn on, volume= 5 ld stop,0x1c ; stpc, d, e turn on, stpa, b turn off voice_304 ; sample rate= 8k, led1 turn off, volume= 4 voice_213 ; sample rate= 6k, led1 turn on, volume= 3 ld stop,0x18 ; stpd, e turn on, stpa, b, c turn off voice_302 ; sample rate= 8k, led1 turn off, volume= 2 ld stop,0x10 ; stpe turn on, stpa, b, c, d turn off voice_211 ; sample rate= 6k, led1 turn on, volume= 1 ld stop,0x00 ; stpa, b, c, d, e turn off voice_300+t4 ; sample rate= 8k, led1 turn off, volume= 0 end example 4: register application this program combines one sentence when tg1 is triggered before. it will then play a sentence with the tg2 voice and tg3 voice. tg2 and tg3 are sequence functions. words for tg2 and tg3 can be chosen and trigger tg1 will play the combined sentence. program: W58105 32: ld en,0x00 ld mode, 0x10 ; pin15 set as stpc output ld stop, 0xff ; set stpa, stpb, stpc, stpd, stpe = 1 ld r1,10 ; set r1, r2, r3, r4 initial data ld r2,20 ld r3,10
w581xx design guide - 39 - ld r4,20 ld en, 0x07 ; enable tg1, tg2, tg3 end 0: ; tg1 plays the combined sentence ld stop,0xfe ; set tg4 low as the combine function flag jp r3 ; play the r3+r4 voice 1: jp r1 ; play sequentially voice1 --> voice2 --> voice3 --> voice1... 2: jp r2 ; play sequentially voice4 --> voice5 --> voice6 --> voice4... 10: ld r1, 11 ld r3, 10 h4+i+am+t4 ; voice1 jp r4 @tg4_low end 11: ld r1, 12 ld r3, 11 h4+you+are+t4 ; voice2 jp r4 @tg4_low end 12: ld r1, 10 ld r3, 12 h4+she+is+t4 ; voice3 jp r4 @tg4_low end 20: ld r2, 21 ld r4, 20 ld stop, 0xff ; set stpa, stpb, stpc, stpd, stpe = 1 h4+a+pretty+woman+t4 ; voice4 end 21: ld r2, 22 ld r4, 21 ld stop, 0xff ; set stpa, stpb, stpc, stpd, stpe = 1 h4+an+ugly+girl+t4 ; voice5 end 22: ld r2, 20
w581xx design guide - 40 - ld r4, 22 ld stop, 0xff ; set stpa, stpb, stpc, stpd, stpe = 1 h4+a+fat+lady+t4 ; voice6 end application circuit tg1 tg2 tg3 w581xx aud tg4 led1 sta stb v dd
w581xx design guide - 41 - revision history version date writer reasons for change e april 22nd, 1999 sophia ho modify cpu mode and add an example of 4bit control program

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